Performance analysis of low power 6T SRAM cell in 180nm and 90nm

Author:

Kumar C Ashok,Madhavi B K,Lalkishore K

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of Low Power and Robust Asynchronous SRAM Generated Using AMC Involving SAHB Circuit with QDI Logic;Journal of The Institution of Engineers (India): Series B;2024-03-26

2. Seepage Power Aware SBVL Based FinFET Design for SRAM Construction;2023 International Conference on Ambient Intelligence, Knowledge Informatics and Industrial Electronics (AIKIIE);2023-11-02

3. Performance Analysis of 9T SRAM using 180nm, 90nm, 65nm, 32nm, 14nm CMOS Technologies;International Journal of Electrical and Electronics Research;2022-06-30

4. An Open-Source RRAM Compiler;2022 20th IEEE Interregional NEWCAS Conference (NEWCAS);2022-06-19

5. In 12nm FinFET Technology, performance analysis of low power 6T SRAM layout designs with two different topologies;2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS);2022-05-23

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