Design of 32nm Phase locked loop for 5G Technology
Author:
Affiliation:
1. Symbiosis Institute of Technology, Symbiosis International Deemed University,Dept. Electronics and Telecommunication,Pune,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9752769/9752688/09752787.pdf?arnumber=9752787
Reference15 articles.
1. Design and analysis of improved performance ring VCO based on differential pair configuration
2. Low power design of ultra wideband PLL using 90 nm CMOS technology
3. Design and Analysis of Low Power and High Frequency Current Starved Sleep Voltage Controlled Oscillator for Phase Locked Loop Application
4. Low Power Ring Oscillator at 180nm CMOS Technology
5. Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
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1. Design of a Configurable Digital Phase Locked Loop Circuit;2023 9th Annual International Conference on Network and Information Systems for Computers (ICNISC);2023-10-27
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