An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-ps<sub>rms</sub>-Integrated-Jitter Degradation With SSC Capability-Reference-Cited by-同舟云学术

An Attachable Fractional Divider Transforming an Integer-N PLL Into a Fractional-N PLL Achieving Only 0.35-ps_rms-Integrated-Jitter Degradation With SSC Capability

Published:2023 Issue: Volume:6 Page:69-72
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Motozawa Atsushi¹^ORCID,Hiraku Yasuyuki¹,Hirai Yoshitaka¹,Hiyama Naoaki¹,Imanaka Yusuke¹,Morishita Fukashi¹^ORCID

Affiliation:

1. IoT and Infrastructure Business Unit, Renesas Electronics Corporation, Tokyo, Japan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/10016898/10064335.pdf?arnumber=10064335

Reference13 articles.

1. A 2-to-2.48GHz voltage-interpolator-based fractional-N type-I sampling PLL in 22nm FinFET assisting fast crystal startup;kundu;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2022

2. A 188fsrms-jitter and–243dB-FoMjitter 5.2GHz-Ring-DCO-based fractional-N digital PLL with a 1/8 DTC-range-reduction technique using a quadruple-timing-margin phase selector;hwang;IEEE Int Solid-State Circuits Conf,2022

3. A 32-Step Phase-Compensated Spread-Spectrum RF-PLL With 19.44-dB EMI Reduction and 10-fs Extra RMS Jitter

4. A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -65 dBc In-Band Fractional Spur

5. A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider

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