An Input Insensitive Quantization Error Extraction Circuit for 8-MHz-BW 79-dB-DR CT MASH Delta–Sigma ADC With Multi-rate LMS-Based Background Calibration-Reference-Cited by-同舟云学术

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An Input Insensitive Quantization Error Extraction Circuit for 8-MHz-BW 79-dB-DR CT MASH Delta–Sigma ADC With Multi-rate LMS-Based Background Calibration

Published:2020 Issue: Volume:3 Page:398-401
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Fukazawa Mitsuya^ORCID,Fujiwara Masaki,Ochi Atsushi,Alsubaie Raed,Matsui Tetsuo^ORCID

Funder

Renesas Electronics Corporation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/8952828/09197713.pdf?arnumber=9197713

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The design of ΔΣ-ADC in MEMS gyro interface ASIC;Microelectronics Journal;2023-04

2. A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS;IEEE Journal of Solid-State Circuits;2022-12

3. Digital Noise-Cancellation Circuit Implementation Using Proposed Algorithm and Karnaugh Map in a MASH 2-1 Delta-Sigma Modulator;Journal of Circuits, Systems and Computers;2022-06-24

4. Continuous-Time Pipelined Analog-to-Digital Converters: A Mini-Tutorial;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-03

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