Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Cited by
78 articles.
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1. Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07
2. Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design;WSEAS TRANSACTIONS ON SYSTEMS;2024-04-09
3. A Novel 1-bit Fast and Low Power 17-T Full Adder Circuit;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
4. Design of Full Adder Circuits with Optimized Power and Speed Using CMOS Technique;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24
5. A Novel 1-bit Fast and Low Power 19-T Full Adder Circuit at 45 nm Technology Node;2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS);2024-02-24