Numerical Evaluation of the Gate Stacked GNR FET for improved Device Switching
Author:
Affiliation:
1. Delhi Technological University,Microelectronics Research lab,Department of Applied Physics,Delhi,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10093234/10093245/10093656.pdf?arnumber=10093656
Reference20 articles.
1. Analog and RF Performance Evaluation of Junctionless Accumulation Mode (JAM) Gate Stack Gate All Around (GS-GAA) FinFET
2. Performance Comparison of Graphene Nanoribbon FETs With Schottky Contacts and Doped Reservoirs
3. Graphene nanoribbon field effect transistors analysis and applications
4. TCAD investigation of ferroelectric based substrate MOSFET for digital application;mann;Silicon,2021
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