An Automatic Chip-Package Co-Design Flow for Multi-core Neuromorphic Computing SiPs-Reference-Cited by-同舟云学术

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An Automatic Chip-Package Co-Design Flow for Multi-core Neuromorphic Computing SiPs

Published:2020-12-02 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC)
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Author:

Lan Jingjing,Nambiar Vishnu P.,Sabapathy Rheeshaalaen,Dutta Rahul,Chong Chai Tai,Rotaru Mihai Dragos,Lin Kuang Kuo,Bhattacharya Surya,Chai Kevin Tshun Chuan,Do Anh Tuan

Funder

Agency for Science, Technology and Research (A*STAR)

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9314953/9314863/09315089.pdf?arnumber=9315089

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Survey on chiplets: interface, interconnect and integration methodology;CCF Transactions on High Performance Computing;2022-03

2. Chiplet-based Architecture Design for Multi-Core Neuromorphic Processor;2021 IEEE 23rd Electronics Packaging Technology Conference (EPTC);2021-12-07

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