Wafer Level Fine-Pitch Hybrid Bonding: Challenges and Remedies
Author:
Funder
Agency for Science, Technology and Research (A*STAR)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9314953/9314863/09315002.pdf?arnumber=9315002
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Cu pad surface height evaluation technique by in-line SEM for wafer hybrid bonding;Metrology, Inspection, and Process Control XXXVIII;2024-04-10
2. Cu and barrier CMP process development with fine 1μm Cu bond pad and 2.5 μm pitch for Wafer-to-wafer Hybrid Bonding;2023 IEEE 25th Electronics Packaging Technology Conference (EPTC);2023-12-05
3. Pixel-Parallel Three-Layer Stacked CMOS Image Sensors Using Double-Sided Hybrid Bonding of SOI Wafers;IEEE Transactions on Electron Devices;2023-09
4. Potassium hydroxide surface modification for low temperature Cu/SiO2 hybrid bonding;Surfaces and Interfaces;2023-08
5. Fine-pitch <111>-oriented NT-Cu/SiO2 hybrid joints with high thermal fatigue resistance and low contact resistivity;2023 International Conference on Electronics Packaging (ICEP);2023-04-19
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