Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
24 articles.
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1. P-TICER: An Effective Parallel TICER Acceleration Method for Model Order Reduction;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
2. CMOS substrate RC netlist reduction towards design cycle speed up;AEU - International Journal of Electronics and Communications;2023-11
3. Improve Sparse Implicit Projection Via Incomplete Cholesky Factorization;2023 China Semiconductor Technology International Conference (CSTIC);2023-06-26
4. Average-Approximation SIP Algorithms Used to Improve Accuracy of RC Model Order Reduction;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08
5. Realizable Reduction of Multi-Port RCL Networks by Block Elimination;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-01