An industrially effective environment for formal hardware verification-Reference-Cited by-同舟云学术

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An industrially effective environment for formal hardware verification

Published:2005-09 Issue:9 Volume:24 Page:1381-1405
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Seger C.-J.H.,Jones R.B.,O'Leary J.W.,Melham T.,Aagaard M.D.,Barrett C.,Syme D.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/32228/01501903.pdf?arnumber=1501903

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Invited: A Scalable Formal Approach for Correctness-Assured Hardware Design;2023 60th ACM/IEEE Design Automation Conference (DAC);2023-07-09

2. Parameterized Design and Formal Verification of Multi-ported Memory;2022 26th International Conference on Engineering of Complex Computer Systems (ICECCS);2022-03

3. Timed Causal Fanin Analysis for Symbolic Circuit Simulation;Form Comp Aid Design;2022

4. Verification of Arithmetic and Datapath Circuits with Symbolic Simulation;Handbook of Computer Architecture;2022

5. Formal Verification of Complex Data Paths: An Industrial Experience;Formal Methods;2021

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