Author:
Khandelwal Vishal,Srivastava Ankur
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software
Cited by
8 articles.
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1. Clock Skew Optimization for Voltage Variation;2019 China Semiconductor Technology International Conference (CSTIC);2019-03
2. Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2018-02
3. Delay Locking;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
4. A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2015-07
5. Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2014-08