High speed LVDS driver for SERDES

Author:

Gupta H.S.,Parmar R.M.,Dave R.K.

Publisher

IEEE

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Wide Common Mode LVDS Receiver Architecture Design and Analysis in 18nm FinFET Technology;2023 IEEE World Conference on Applied Intelligence and Computing (AIC);2023-07-29

2. Analysis of Serializer for High Speed Transmission;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28

3. A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control and Jitter Estimation;IEICE Transactions on Electronics;2020-10-01

4. A Robust Architecture Based on Adaptive Recursive Filter for Gigabit Communications;Lecture Notes in Electrical Engineering;2020-06-24

5. A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology;Electronics;2019-03-22

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