Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor
Author:
Affiliation:
1. Tezpur University,Department of Electronics and Communication Engineering,Assam,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10483275/10483296/10483528.pdf?arnumber=10483528
Reference14 articles.
1. Low-Leakage-Current DRAM-Like Memory Using a One-Transistor Ferroelectric MOSFET With a Hf-Based Gate Dielectric
2. Ferroelectricity in hafnium oxide thin films
3. Drain–Erase Scheme in Ferroelectric Field-Effect Transistor—Part I: Device Characterization
4. Drain-Erase Scheme in Ferroelectric Field Effect Transistor—Part II: 3-D-NAND Architecture for In-Memory Computing
5. Disturb-Free Operations of Multilevel Cell Ferroelectric FETs for Nand Applications
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