A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier-Reference-Cited by-同舟云学术

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A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier

Published:2021 Issue: Volume: Page:1-1
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zheng Zihao,Wei Lai,Lagos Jorge,Martens Ewout,Zhu Yan,Chan Chi-Hang,Craninckx Jan,Martins Rui P.

Funder

Science and Technology Development Fund Macau

Research Grants of the University of Macau

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/4359912/09495934.pdf?arnumber=9495934

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS;IEEE Journal of Solid-State Circuits;2024-03

2. A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS;IEEE Access;2024

3. A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage;IEEE Journal of Solid-State Circuits;2024

4. A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

5. A 0.004-mm² 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS;IEEE Journal of Solid-State Circuits;2023-11

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