Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks-Reference-Cited by-同舟云学术

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Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

Published:2021-07 Issue:7 Volume:56 Page:2221-2233
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kim Hyunjoon^ORCID,Yoo Taegeun^ORCID,Kim Tony Tae-Hyoung^ORCID,Kim Bongjin^ORCID

Funder

RIE2020 ASTAR AME IAF-ICP

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9466892/09373949.pdf?arnumber=9373949

Cited by 90 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-08

2. A Resonant Time-Domain Compute-in-Memory (rTD-CiM) ADC-Less Architecture for MAC Operations;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

3. A DRAM-based Near-Memory Architecture for Accelerated and Energy-Efficient Execution of Transformers;Proceedings of the Great Lakes Symposium on VLSI 2024;2024-06-12

4. High energy efficient and configurable CIM macro for image processing;Microelectronics Journal;2024-06

5. SRAM-Based Digital CIM Macro for Linear Interpolation and MAC;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

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