TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization-Reference-Cited by-同舟云学术

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization

Published:2023-03 Issue:3 Volume:58 Page:852-866
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Guo Ruiqi¹^ORCID,Yue Zhiheng¹^ORCID,Si Xin²^ORCID,Li Hao¹,Hu Te¹,Tang Limei¹,Wang Yabing¹,Sun Hao¹,Liu Leibo¹^ORCID,Chang Meng-Fan³^ORCID,Li Qiang⁴^ORCID,Wei Shaojun¹^ORCID,Yin Shouyi¹^ORCID

Affiliation:

1. Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, and the Beijing Advanced Innovation Center, Tsinghua University, Beijing, China

2. National ASIC System Engineering Research Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China

3. Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan

4. Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China (UESTC), Chengdu, China

Funder

NSFC

National Key Research and Development Program

Beijing Science and Technology Project

Beijing Advanced Innovation Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10051119/09867947.pdf?arnumber=9867947

Reference34 articles.

1. A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors

2. 15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications

3. Recognizing realistic actions from videos “in the wild”

4. 15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing

5. Eyeriss

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