A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping-Reference-Cited by-同舟云学术

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A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping

Published:2021-03 Issue:3 Volume:56 Page:739-749
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Hsu Chen-Kai^ORCID,Tang Xiyuan^ORCID,Liu Jiaxin^ORCID,Xu Rui^ORCID,Zhao Wenda^ORCID,Mukherjee Abhishek^ORCID,Andeen Timothy R.,Sun Nan^ORCID

Funder

NSF

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielam/4/9361453/9286522-aam.pdf

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping;Microelectronics Journal;2024-09

2. A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC;IEEE Journal of Solid-State Circuits;2024-08

3. A Fast and Cost-Effective Calibration Strategy of Inter-Stage Residual Amplification Errors for Cyclic-Pipelined ADCs;Electronics;2024-06-19

4. A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator;IEEE Journal of Solid-State Circuits;2023-12

5. A 77.8dB-SNDR 25MHz-BW 2^nd-order NS Pipelined SAR ADC with 4^th-order Gain-Error-Shaping;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24

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