A Low-Spur and Low-Jitter Fractional-<i>N</i> Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering-Reference-Cited by-同舟云学术

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering

Published:2023-12 Issue:12 Volume:58 Page:3320-3337
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Dartizio Simone M.¹^ORCID,Tesolin Francesco¹^ORCID,Castoro Giacomo¹^ORCID,Buccoleri Francesco¹^ORCID,Rossoni Michele¹,Cherniak Dmytro²,Samori Carlo¹^ORCID,Lacaita Andrea L.¹^ORCID,Levantino Salvatore¹^ORCID

Affiliation:

1. Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy

2. Infineon Technologies AG, Villach, Austria

Funder

Infineon Technologies, Villach

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10328904/10253943.pdf?arnumber=10253943

Reference46 articles.

1. A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter

2. Low jitter design of a 0.35 ?m-CMOS frequency divider operating up to 3 GHz;romano;Proc 28th Eur Solid-State Circuits Conf,2002

3. A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

4. A Wideband 2.4-GHz Delta-Sigma Fractional->tex<$N$>/tex<PLL With 1-Mb/s In-Loop Modulation

5. A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit

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1. Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

2. A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector;2024 IEEE Custom Integrated Circuits Conference (CICC);2024-04-21

3. Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop;IEEE Journal of Solid-State Circuits;2024