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A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation

  • Published:2021-08 Issue:8 Volume:56 Page:2375-2387
  • ISSN:0018-9200
  • Container-title:IEEE Journal of Solid-State Circuits
  • language:
  • Short-container-title:IEEE J. Solid-State Circuits

Author:

Jiang DongyangORCID,Qi LiangORCID,Sin Sai-WengORCID,Maloberti FrancoORCID,Martins Rui P.ORCID

Funder

The Science and Technology Development Fund, Macau SAR

The Ministry of Science and Technology, China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter;Journal of Circuits, Systems and Computers;2024-06-01

2. Comparative Study for Different Loop-Filter Architectures of 2x Time-Interleaved CT DSM;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

3. A 2.3-ppm/℃ High-Order Compensated Bandgap Reference With Low-Cost Current Trimming;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. An Improved DEM for Multibit DT ΣΔMs Based on Poles Splitting Technique and Segmented VQ;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

5. An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process;IEEE Transactions on Circuits and Systems I: Regular Papers;2024
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