A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs-Reference-Cited by-同舟云学术

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A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs

Published:2021-01 Issue:1 Volume:56 Page:225-234
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kouchi Toshiyuki^ORCID,Kakoi Mami,Kumazaki Noriyasu,Sugahara Akio,Imamoto Akihiro,Kajiyama Yasufumi,Terada Yuri,Sanad Bushnaq,Kanagawa Naoaki,Kodama Takuyo,Fukuda Ryo,Komai Hiromitsu,Asaoka Norichika,Ohnishi Hidekazu,Isomura Ryosuke,Handa Takaya,Yamamoto Kensuke^ORCID,Ishizaki Yuki,Deguchi Yoko,Okuyama Atsushi,Sato Junichi,Yabe Hiroki,Hsu Hua-Ling Cynthia,Yoshihara Masahiro

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9306027/09234438.pdf?arnumber=9234438

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Two‐Dimensional Semiconductors: From Device Processing to Circuit Integration;Advanced Functional Materials;2023-08-17

2. Polarized Tunneling Transistor for Ultrafast Memory;ACS Nano;2023-06-20

3. BOOSTER: Rethinking the erase operation of low-latency SSDs to achieve high throughput and less long latency;Proceedings of the 16th ACM International Conference on Systems and Storage;2023-06-05

4. Very Large-Scale Integration Floor Planning on FIR and Lattice Filters Design With Multi-Objective Hybrid Optimization;International Journal of Swarm Intelligence Research;2023-04-20

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