A 3.2-GHz 405 fs<sub>rms</sub> Jitter –237.2 dB FoM<sub>JIT</sub> Ring-Based Fractional-N Synthesizer-Reference-Cited by-同舟云学术

A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer

Published:2022-03 Issue:3 Volume:57 Page:698-708
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Elmallah Ahmed^ORCID,Zhu Junheng^ORCID,Khashaba Amr^ORCID,Megawer Karim M.^ORCID,Elkholy Ahmed^ORCID,Hanumolu Pavan Kumar^ORCID

Funder

Analog Devices

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9718232/09695393.pdf?arnumber=9695393

Reference23 articles.

1. A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation

2. A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-${\rm fs}_{\rm rms}$ Integrated Jitter at 4.5-mW Power

3. A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

4. A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

5. A 0.98 mW fractional-$N$ ADPLL using 10b isolated constant-slope DTC with FOM of –246 dB for IoT applications in 65 nm CMOS;liu;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2018

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