A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS-Reference-Cited by-同舟云学术

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A 1.6ps peak-INL 5.3ns range two-step digital-to-time converter in 65nm CMOS

Published:2018-04 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Custom Integrated Circuits Conference (CICC)
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Author:

Elmallah Ahmed,Ahmed Mostafa Gamal,Elkholy Ahmed,Choi Woo-Seok,Hanumolu Pavan Kumar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8355238/8357004/08357042.pdf?arnumber=8357042

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Resolution-Tunable Low Power Time-to-Digital Converter With an Improved ADDLL Based on a Cyclic Pulse Ring Oscillator;IEEE Transactions on Instrumentation and Measurement;2023

3. A Highly Linear Digitally Controlled Delay Line with Reduced Duty Cycle Distortion;2022 19th International SoC Design Conference (ISOCC);2022-10-19

4. A 3.2-GHz 405 fs_rms Jitter –237.2 dB FoM_JIT Ring-Based Fractional-N Synthesizer;IEEE Journal of Solid-State Circuits;2022-03

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