A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR-Reference-Cited by-同舟云学术

A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24–71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR

Published:2022-12 Issue:12 Volume:57 Page:3617-3630
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Zhang Yi¹^ORCID,Pang Jian¹^ORCID,Li Zheng¹^ORCID,Tang Minzhe¹,Liao Yijing¹,Fadila Ashbir Aviat¹^ORCID,Shirane Atsushi¹,Okada Kenichi¹^ORCID

Affiliation:

1. Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo, Japan

Funder

Ministry of Internal Affairs and Communications in Japan

JST SPRING

STAR

VDEC in collaboration with Cadence Design Systems, Inc.

Mentor Graphics, Inc.

Keysight Technologies Japan, Ltd

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9962295/09924569.pdf?arnumber=9924569

Reference44 articles.

1. A PVT-Tolerant >40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS

2. Analysis and Design of Passive Polyphase Filters

3. Design and Performance of a Wideband Ka-Band 5-b MMIC Phase Shifter

4. 60-GHz Four-Element Phased-Array Transmit/Receive System-in-Package Using Phase Compensation Techniques in 65-nm Flip-Chip CMOS Process

5. A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS

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