A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features-Reference-Cited by-同舟云学术

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features

Published:2023-04 Issue:4 Volume:58 Page:1051-1061
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Ryu Yesin¹^ORCID,Ahn Sung-Gi¹,Lee Jae Hoon¹,Park Jaewon¹,Kim Yong Ki¹^ORCID,Kim Hyochang¹^ORCID,Song Yeong Geol¹,Cho Han-Won¹,Cho Sunghye¹,Song Seung Ho¹,Lee Haesuk¹,Shin Useung¹,Ahn Jonghyun¹,Ryu Je-Min¹,Lee Sukhan¹,Lim Kyoung-Hwan¹,Lee Jungyu¹,Park Jeong Hoan¹,Jeong Jae-Seung¹^ORCID,Joo Sunghwan¹^ORCID,Cho Dajung¹,Kim So Young¹,Lee Minsu¹,Kim Hyunho¹^ORCID,Kim Minhwan¹,Kim Jae-San¹,Kim Jinah¹,Kang Hyun Gil¹,Lee Myung-Kyu¹,Kim Sung-Rae¹,Kwon Young-Cheon¹,Byun Young Yong¹,Lee Kijun¹,Park Sangkil¹,Youn Jaeyoun¹,Kim Myeong-O¹,Sohn Kyomin¹^ORCID,Hwang Sang-Joon¹,Lee Jooyoung¹

Affiliation:

1. Memory Division, Samsung Electronics, Hwaseong, South Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10082904/10005600.pdf?arnumber=10005600

Reference15 articles.

1. HBM3 RAS: Enhancing Resilience at Scale

2. Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook

3. Controllability/observability analysis of digital circuits

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