PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge-Reference-Cited by-同舟云学术

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PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge

Published:2023-07-09 Issue: Volume: Page:
ISSN:
Container-title:2023 60th ACM/IEEE Design Automation Conference (DAC)
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Author:

Jain Vikram¹,Cavalcante Matheus²,Bruschi Nazareno³,Rogenmoser Michael²,Benz Thomas²,Kurth Andreas²,Rossi Davide³,Benini Luca²,Verhelst Marian¹

Affiliation:

1. KU Leuven,ESAT-MICAS,Belgium

2. ETH Zurich,IIS,Switzerland

3. University of Bologna,Italy

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10247654/10247655/10247800.pdf?arnumber=10247800

Reference28 articles.

1. GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors;bruschi;ICCD,2021

2. DepFiN: A 12nm, 3.8TOPs depth-first CNN processor for high res. image processing

3. Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference

4. Noxim: An open, extensible and cycle-accurate network on chip simulator

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