An efficient distributed memory interface for many-core platform with 3D stacked DRAM-Reference-Cited by-同舟云学术

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An efficient distributed memory interface for many-core platform with 3D stacked DRAM

Published:2010-03 Issue: Volume: Page:
ISSN:
Container-title:2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)
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Author:

Loi Igor,Benini Luca

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5450668/5456897/05457230.pdf?arnumber=5457230

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM;2022 19th International SoC Design Conference (ISOCC);2022-10-19

2. 3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems;International Journal of Parallel Programming;2017-04-11

3. A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D–Stacked Architecture;Journal of Signal Processing Systems;2016-12-03

4. BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories;Journal of Computer Science and Technology;2016-01

5. Analyzing the Trade-off Between Different Memory Cores and Controllers;Analog Circuits and Signal Processing;2016

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