A unified methodology for pre-silicon verification and post-silicon validation-Reference-Cited by-同舟云学术

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A unified methodology for pre-silicon verification and post-silicon validation

Published:2011-03 Issue: Volume: Page:
ISSN:
Container-title:2011 Design, Automation & Test in Europe
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Author:

Adir A,Copty S,Landa S,Nahir A,Shurek G,Ziv A,Meissner C,Schumann J

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5754459/5762992/05763252.pdf?arnumber=5763252

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synthetic Benchmark for Data-Driven Pre-Si Analogue Circuit Verification;Electronics;2024-07-02

2. Prognostics for Semiconductor Sustainability: Tool Failure Behavior Prediction in Fabrication Processes;IEEE Transactions on Systems, Man, and Cybernetics: Systems;2024-06

3. Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

4. Pre-Silicon Verification and Post-Silicon Validation Methodologies;Synthesis Lectures on Digital Circuits & Systems;2024

5. VLSI Design Course with Verification of RISC-V Design using Universal Verification Methodology (UVM);2022 IEEE 12th International Conference on Control System, Computing and Engineering (ICCSCE);2022-10-21

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