Author:
Jie Jiang ,Sauer M.,Czutro A.,Becker B.,Polian I.
Cited by
3 articles.
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1. Path Unselection for Path Delay Fault Test Generation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02
2. Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-12
3. Selecting Path Delay Faults Through the Largest Subcircuits of Uncovered Lines;2022 IEEE 31st Asian Test Symposium (ATS);2022-11