High-speed on-chip ECC for synergistic fault-tolerance memory chips-Reference-Cited by-同舟云学术

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High-speed on-chip ECC for synergistic fault-tolerance memory chips

Published:1991 Issue:10 Volume:26 Page:1449-1452
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Fifield J.A.,Stapper C.H.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/2985/00090100.pdf?arnumber=90100

Cited by 17 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Introduction;Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design;2023

2. GPU-Based ECC Decode Unit for Efficient Massive Data Reception Acceleration;J INF PROCESS SYST;2020

3. Combination of Redundancy and Error Correction;Integrated Circuits and Systems;2010-11-26

4. Variation-tolerant hierarchical voltage monitoring circuit for soft error detection;2009 10th International Symposium on Quality of Electronic Design;2009-03

5. A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC;IEICE Transactions on Electronics;2006-11-01

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