An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Signal Processing
Link
http://xplorestaging.ieee.org/ielx7/78/6817662/06803952.pdf?arnumber=6803952
Cited by 38 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers;IEEE Access;2024
2. Implementation of Successive Cancellation Polar Decoder Architecture;2023 IEEE 20th India Council International Conference (INDICON);2023-12-14
3. Overview of various methods for decoding and constructing critical sets of polar codes;Journal of Communications and Networks;2023-12
4. Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-03
5. Efficient Partial Rewind of Successive Cancellation-Based Decoders for Polar Codes;IEEE Transactions on Communications;2022-11
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