Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers-Reference-Cited by-同舟云学术

Efficient Hardware Realization of SC Polar Decoders Using Compound Pipelined Processing Units and Auxiliary Registers

Published:2024 Issue: Volume:12 Page:23808-23826
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Ali Yasir¹^ORCID,Xia Yuanqing¹^ORCID,Manzoor Tayyab²^ORCID,Ali Shahzad¹^ORCID,Abouhawwash Mohamed³^ORCID,Askar S. S.⁴^ORCID,Kumar Amit Krishan⁵^ORCID,Ma Ruifeng¹^ORCID

Affiliation:

1. School of Automation, Beijing Institute of Technology, Beijing, China

2. School of Automation and Electrical Engineering, Zhongyuan University of Technology, Zhengzhou, China

3. Department of Mathematics, Faculty of Science, Mansoura University, Mansoura, Egypt

4. Department of Statistics and Operations Research, College of Science, King Saud University, Riyadh, Saudi Arabia

5. Institute of Research and Development, Duy Tan University, Da Nang, Vietnam

Funder

King Saud University, Riyadh, Saudi Arabia. Researchers Supporting Project number

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/6287639/10380310/10430153.pdf?arnumber=10430153

Reference43 articles.

1. Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels

2. A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation

3. High-Throughput Adaptive List Decoding Architecture for Polar Codes on GPU

4. Secure design for cloud control system against distributed denial of service attack

5. Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing

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