Implementation of fully self-aligned bottom-gate MOS transistor-Reference-Cited by-同舟云学术

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Implementation of fully self-aligned bottom-gate MOS transistor

Published:2002-10 Issue:10 Volume:23 Page:618-620
ISSN:0741-3106
Container-title:IEEE Electron Device Letters
language:
Short-container-title:IEEE Electron Device Lett.

Author:

Shengdong Zhang ,Ruqi Han ,Zhikuan Zhang ,Ru Huang ,Ko P.K.,Mansun Chan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx5/55/22270/01039186.pdf?arnumber=1039186

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-Performance Top-Gated and Double-Gated Oxide–Semiconductor Ferroelectric Field-Effect Transistor Enabled by Channel Defect Self-Compensation Effect;IEEE Transactions on Electron Devices;2023-04

2. High-Performance Self-Aligned Bottom-Gate Low-Temperature Poly-Silicon Thin-Film Transistors With Excimer Laser Crystallization;IEEE Electron Device Letters;2007-07

3. A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM;IEEE Transactions on Electron Devices;2003-09

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