Parallel LDPC Decoder Based on Low-Complexity Corrected Min Sum Algorithm-Reference-Cited by-同舟云学术

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Parallel LDPC Decoder Based on Low-Complexity Corrected Min Sum Algorithm

Published:2022-04-22 Issue: Volume: Page:
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Container-title:2022 4th International Conference on Advances in Computer Technology, Information Science and Communications (CTISC)
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Author:

Sun Yisong¹,Li Huan²,Zhang Xinyu³,Guo Chen²,Liu Zijun²,Wang Donglin²

Affiliation:

1. University of Chinese Academy of Sciences (UCAS),Institute of Automation, Chinese Academy of Sciences (CASIA),Beijing,China

2. Chinese Academy of Sciences (CAS),Institute of Automation, Chinese Academy of Sciences (CASIA),Beijing,China

3. Beijing Smart Logic East Technology Co., Ltd.,Department of Applied Algorithm,Beijing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9849705/9849682/09849693.pdf?arnumber=9849693

Reference10 articles.

1. Fast DSP Implementation of a Low Complexity LDPC Decoder

2. NR; Multiplexing and channel coding,2020

3. An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

4. Reduced complexity iterative decoding of low-density parity check codes based on belief propagation

5. LDPC decoder implementation on DSP+ARM platform with OpenCL

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