An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder
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Published:2021-12-01
Issue:6
Volume:11
Page:4774
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ISSN:2722-2578
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Container-title:International Journal of Electrical and Computer Engineering (IJECE)
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language:
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Short-container-title:IJECE
Author:
Razi Mouhcine,Benhayoun Mhammed,Mansouri Anass,Ahaitouf Ali
Abstract
<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms. In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF). An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>
Publisher
Institute of Advanced Engineering and Science
Subject
Electrical and Electronic Engineering,General Computer Science
Cited by
3 articles.
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1. Reliability-Based Single Bit-Flipping Decoding Algorithm for LDPC Codes;Lecture Notes in Electrical Engineering;2024
2. Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications;Applied Computational Intelligence and Soft Computing;2023-10-21
3. Parallel LDPC Decoder Based on Low-Complexity Corrected Min Sum Algorithm;2022 4th International Conference on Advances in Computer Technology, Information Science and Communications (CTISC);2022-04-22