Low-power CMOS at Vdd=4kT/q-Reference-Cited by-同舟云学术

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Low-power CMOS at Vdd=4kT/q

Published: Issue: Volume: Page:
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Container-title:Device Research Conference. Conference Digest (Cat. No.01TH8561)
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Author:

Bryant A.,Brown J.,Cottrell P.,Ketchen M.,Ellis-Monaghan J.,Nowak E.J.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7459/20292/00937856.pdf?arnumber=937856

Cited by 25 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A brief Survey of Ultra-Low-Voltage CMOS: Approaching the Diffusion Limit;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27

2. Bridging the Gap between Design and Simulation of Low-Voltage CMOS Circuits;Journal of Low Power Electronics and Applications;2022-06-16

3. Analysis and Design of the Three-Inverter Schmitt Trigger for Supply Voltages Down to 50 mV;IEEE Transactions on Circuits and Systems II: Express Briefs;2021-07

4. Ultra Low Voltage Sub-100 mV Vdd CMOS;2021 19th IEEE International New Circuits and Systems Conference (NEWCAS);2021-06-13

5. Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders;2020 IEEE Nordic Circuits and Systems Conference (NorCAS);2020-10-27

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