A brief Survey of Ultra-Low-Voltage CMOS: Approaching the Diffusion Limit-Reference-Cited by-同舟云学术

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A brief Survey of Ultra-Low-Voltage CMOS: Approaching the Diffusion Limit

Published:2024-02-27 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS)
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Author:

Galup-Montoro Carlos¹,Schneider Marcio Cherem¹,Fernandes Thiago Darós¹,Alves Neto Deni Germano¹

Affiliation:

1. Federal University of Santa Catarina,Department of Electrical and Electronics Engineering,Florianópolis,SC,Brazil

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10506108/10506116/10506162.pdf?arnumber=10506162

Reference22 articles.

1. Ion-implanted complementary MOS transistors in low-voltage circuits

2. Low-power CMOS at Vdd=4kT/q

3. A 62 mV 0.13 $\mu$m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic

4. Comparison and optimization of the minimum supply voltage of Schmitt trigger gates versus CMOS gates under process variations;Bleitner,2018

5. An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V

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