A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR
Author:
Affiliation:
1. University of Virginia,Charlottesville,VA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10121189/10121178/10121253.pdf?arnumber=10121253
Reference7 articles.
1. Low Power Radio Survey;wentzloff,0
2. A Dual-Mode Wi-Fi/BLE WakeUp Receiver;wang;JSSC,2021
3. A 2.4 GHz-91.5 dBm Sensitivity WithinPacket Duty-Cycled Wake-Up Receiver;dissanayake;JSSC,2022
4. An LPWAN Radio with a Reconfigurable Data/Duty-Cycled-Wake-Up Receiver
5. A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL;IEEE Open Journal of the Solid-State Circuits Society;2024
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