On the reuse of existing error tolerance circuitry for low power scan testing-Reference-Cited by-同舟云学术

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On the reuse of existing error tolerance circuitry for low power scan testing

Published:2015-05 Issue: Volume: Page:
ISSN:
Container-title:2015 IEEE International Symposium on Circuits and Systems (ISCAS)
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Author:

Anastasiou Anthi,Tsiatouhas Yiorgos,Arapoyanni Angela

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7152138/7168553/07168949.pdf?arnumber=7168949

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-03

2. An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits;2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD);2021-11-01

3. Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template;2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2020-05

4. Testing the blade resilient asynchronous template;Analog Integrated Circuits and Signal Processing;2020-04-23

5. An LSSD Compliant Scan Cell for Flip-Flops;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018

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