Efficient Message Passing Architecture for High Throughput LDPC Decoder-Reference-Cited by-同舟云学术

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Efficient Message Passing Architecture for High Throughput LDPC Decoder

Published:2007-05 Issue: Volume: Page:
ISSN:
Container-title:2007 IEEE International Symposium on Circuits and Systems
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Author:

Cui Zhiqiang,Wang Zhongfeng

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4252534/4252535/04252785.pdf?arnumber=4252785

Cited by 10 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Normalized Min-Sum Neural Network for LDPC Decoding;IEEE Transactions on Cognitive Communications and Networking;2023-02

2. VLSI Design for Low-Density Parity-Check Code Decoding;IEEE Circuits and Systems Magazine;2011

3. A Split-Decoding Message Passing Algorithm for Low Density Parity Check Decoders;Journal of Signal Processing Systems;2010-02-26

4. Flexible LDPC Decoder Design for Multigigabit-per-Second Applications;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-01

5. Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes;IEEE Transactions on Circuits and Systems I: Regular Papers;2010-01

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