An Ultra-low-power True Single-phase Clocking Flip-flop with Improved Hold time Variation using Logic Structure Reduction Scheme
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8334884/8350884/08350985.pdf?arnumber=8350985
Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application;IEICE Electronics Express;2023-12-10
2. A novel high-speed low-power sense-amplifier-based flip-flop for digital circuits application;IEICE ELECTRON EXPR;2023
3. Design Automation of Series Resonance Clocking in 14-nm FinFETs;Circuits, Systems, and Signal Processing;2023-08-01
4. An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
5. Review of Different Flip-Flop Circuits and a Modified Flip-Flop Circuit for Low Voltage Operation;2022 IEEE 3rd Global Conference for Advancement in Technology (GCAT);2022-10-07
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