3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules-Reference-Cited by-同舟云学术

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3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules

Published:1992-03 Issue:3 Volume:27 Page:373-381
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Yano K.,Hiraki M.,Shukuri S.,Hanawa M.,Suzuki M.,Morita S.,Kawamata A.,Ohki N.,Nishida T.,Seki K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/3460/00121560.pdf?arnumber=121560

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. BiCMOS On-Chip Drivers;Advanced Low-Power Digital Circuit Techniques;1997

2. A 64-bit carry look ahead adder using pass transistor BiCMOS gates;IEEE Journal of Solid-State Circuits;1996-06

3. A 4.4 ns CMOS 54×54-b multiplier using pass-transistor multiplexer;IEEE Journal of Solid-State Circuits;1995-03

4. Analysis of BiCMOS buffer for input voltages with finite rise time;IEEE Journal of Solid-State Circuits;1994-07

5. Modeling the d.c. characteristics of merged bipolar-MOS structures;Solid-State Electronics;1994-03

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