Double Adjacent Error Correction in RRAM Matrix Multiplication using Weighted Checksums-Reference-Cited by-同舟云学术

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Double Adjacent Error Correction in RRAM Matrix Multiplication using Weighted Checksums

Published:2024-07-03 Issue: Volume: Page:1-5
ISSN:
Container-title:2024 IEEE 30th International Symposium on On-Line Testing and Robust System Design (IOLTS)
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Author:

Pinto Kenrick Xavier¹,Kodali Krishnaja¹,Das Abhishek²,Touba Nur A.¹

Affiliation:

1. University of Texas at Austin

2. Intel Corporation

Funder

National Science Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx8/10616000/10616049/10616083.pdf?arnumber=10616083

Reference11 articles.

1. Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives

2. Time Complexity of In-Memory Matrix-Vector Multiplication

3. Design of fault-tolerant neuromorphic computing systems

4. Stuck-at Fault Tolerance in RRAM Computing Systems

5. Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs

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