Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs-Reference-Cited by-同舟云学术

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Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs

Published:2009-01 Issue:1 Volume:28 Page:111-120
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Bahukudumbi Sudarshan,Chakrabarty Krishnendu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/4723629/04723640.pdf?arnumber=4723640

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-10

2. An Optimization Mechanism for Mid-Bond Testing of TSV-Based 3D SoCs;IEICE Transactions on Electronics;2016

3. Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing;2015 IEEE 24th North Atlantic Test Workshop;2015-05

4. A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability;IEEE Transactions on Reliability;2015-03

5. Dual-Speed TAM Optimization of 3D SoCs for Mid-bond and Post-bond Testing;2014 IEEE 23rd Asian Test Symposium;2014-11

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