An Optimization Mechanism for Mid-Bond Testing of TSV-Based 3D SoCs
Author:
Affiliation:
1. Department of Computer Science, Tsinghua University
2. School of Software, Tsinghua University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E99.C/2/E99.C_308/_pdf
Reference30 articles.
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2. [2] R.S. Patti, “Three-dimensional integrated circuits and the future of system-on-chip designs,” Proc. IEEE, vol.94, no.6, pp.1214-1224, 2006.
3. [3] Y. Xie, G.H. Loh, B. Black, and K. Bernstein, “Design space exploration for 3d architectures,” ACM J. Emerging Technologies in Computing Systems (JETC), vol.2, no.2, pp.65-103, 2006.
4. [4] B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. Sabuncuoglu Tezcan, Z. Tokei, et al., “3d integration by cu-cu thermo-compression bonding of extremely thinned bulk-si die containing 10 µm pitch through-si vias,” Electron Devices Meeting, 2006. IEDM'06. International, pp.1-4, IEEE, 2006.
5. [5] W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, and P.D. Franzon, “Demystifying 3d ics: the pros and cons of going vertical,” Design & Test of Computers, IEEE, vol.22, no.6, pp.498-510, 2005.
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