Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources-Reference-Cited by-同舟云学术

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Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources

Published:2007-11 Issue:11 Volume:26 Page:2046-2058
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Manich Salvador,Garcia-Deiros Lucas,Figueras Joan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx5/43/4351994/04352009.pdf?arnumber=4352009

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Test Time Optimization by Revisiting Notes in VLSI BIST Technique;3C Tecnología_Glosas de innovación aplicadas a la pyme;2020-03-23

2. Accumulator Based 3-Weight Pattern Generation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2012-02

3. An Accumulator—Based Test-Per-Clock Scheme;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2011-06

4. A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences;VLSI Design;2008-03-17

5. Ant colony based efficient triplet calculation methodology for arithmetic built-in self test;IEICE Electronics Express;2008

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