Synthesizable ADPLL Generator: From Specification to GDS
Author:
Affiliation:
1. University of Michigan,Electrical Engineering and Computer Science,Ann Arbor,Michigan
Funder
Advanced Research Projects Agency
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10192100/10192102/10192175.pdf?arnumber=10192175
Reference11 articles.
1. Phase-domain all-digital phase-locked loop
2. A calibration-free 800MHz fractional-N digital PLL with embedded TDC
3. Circuits and Techniques for Cell-based Analog Design Automation in Advanced Processes;moore;Doctoral dissertation,2018
4. An Open Source Compatible Framework to Fully Autonomous Digital LDO Generation
5. A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm
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