A Parallel and Pipelined Hardware Architecture for Fractional-Pixel Motion Estimation in AVS3

Author:

Zeng Yuning1,Zhu Xizhong2,Xiang Guoqing3,Hao Zhijian4,Zhang Peng3,Huang Xiaofeng5,Yan Wei1

Affiliation:

1. Peking University,School of Software and Microelectronics,Beijing,China

2. Peking University Shenzhen Guraduate School,School of Electronic and Computer Engineering,Shenzhen,China

3. Peking University,Advanced Institute of Information Technology,Hangzhou,China

4. Fudan University,State Key Laboratory of ASIC & System,Shanghai,China

5. Hangzhou Dianzi University,School of Communication Engineering,Hangzhou,China

Funder

Natural Science Foundation of Zhejiang Province

Publisher

IEEE

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Fast CTU-level SAO Algorithm and Its Hardware Architecture for AVS3 Video Coding;2024 IEEE International Conference on Consumer Electronics (ICCE);2024-01-06

2. A Fast Adaptive Motion Vector Resolution Algorithm for AVS3;2024 IEEE International Conference on Consumer Electronics (ICCE);2024-01-06

3. A Hardware-efficient Unified Motion Estimation for Video Coding;Proceedings of the 31st ACM International Conference on Multimedia;2023-10-26

4. An Efficient Real-Time Hardware Architecture for Deblocking Filter in AVS3;2023 IEEE International Conference on Multimedia and Expo (ICME);2023-07

5. A Hardware-friendly CTU-level IME Algorithm for VVC;2023 Data Compression Conference (DCC);2023-03

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