An Efficient Real-Time Hardware Architecture for Deblocking Filter in AVS3
Author:
Affiliation:
1. Peking University,School of Computer Science,Beijing,China
2. Hangzhou Dianzi University,School of Communication Engineering,Hangzhou,China
3. Peking University,Advanced Institute of Information Technology,Hangzhou,China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10219544/10219545/10219717.pdf?arnumber=10219717
Reference15 articles.
1. A Combined Deblocking Filter and SAO Hardware Architecture for HEVC
2. The VLSI Architecture of a Highly Efficient Deblocking Filter for HEVC Systems
3. A 1062mpixels/s 8192x4320p high efficiency video coding (h.265) encoder chip;tsai;2013 Symposiumon VLSI Circuits,2013
4. A High-Throughput and Multi-Parallel VLSI Architecture for HEVC Deblocking Filter
5. A hardware-efficient deblocking filter design for HEVC
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