Half-swing clocking scheme for 75% power saving in clocking circuitry

Author:

Kojima H.,Tanaka S.,Sasaki K.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. An Overview of Low-Power VLSI Design Methods for CMOS and CNTFET-Based Circuits;2023 International Conference on Computer Communication and Informatics (ICCCI);2023-01-23

2. Energy Efficient Design Techniques in Next-Generation Wireless Communication Networks: Emerging Trends and Future Directions;Wireless Communications and Mobile Computing;2020-03-03

3. A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving;IEEE Journal of Solid-State Circuits;2014-11

4. Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors;IEEE Transactions on Circuits and Systems I: Regular Papers;2012-03

5. Capacitive load balancing for mobius implementation of standing wave oscillator;2009 52nd IEEE International Midwest Symposium on Circuits and Systems;2009-08

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