Author:
Abbaspour S.,Fatemi H.,Pedram M.
Cited by
6 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Path Delay Under Process Variations;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018
2. Gate Delay Under Process Variations;Timing Performance of Nanometer Digital Circuits Under Process Variations;2018
3. Considering Crosstalk Effects in Statistical Timing Analysis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2014-02
4. Efficient and realistic statistical worst case delay computation using VHDL;Electrical Engineering;2009-11-06
5. Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2007-11